1. Field of the Invention
The presents invention relates to a semiconductor device having a huge wiring structure portion on a minute wiring structure portion including wiring layers and insulating layers, each of the wiring layers and each of the insulating layers being alternately laminated, the huge wiring structure portion including wiring layers having thicker than the wiring layer of the minute wiring structure portion and insulating layers having thicker than the insulating layer of the minute wiring structure portion, and the wiring layers and the insulating layers of the huge wiring structure portion being alternately laminated.
2. Description of the Related Art
In connection with miniaturization and highly functional design of electronic equipment, miniaturization and high densification of wirings have been recently required of semiconductor chips. For example, in a microprocessor designed on the basis of the 130 nm rule, the clock frequency thereof reaches several GHz and the driving current thereof reaches 100 A, and performance enhancement of the conventional wiring technique is being pushed to the limit. In order to implement a microprocessor having a clock frequency exceeding 10 GHz and a driving current reaching several hundreds A, a wiring technique having a novel structure is required.
For example, K. Kikuchi, et al., “A Package-process-oriented Multilevel 5-μm-thick Cu Wiring Technology with Pulse Periodic Reverse Electroplating and Photosensitive Resin,” Proceeding of the IEEE 2003 International Interconnect Technology Conference (United States of America), Jun. 2003, p. 189-191 discloses such a technique that a huge wiring structure portion comprising huge wires formed of copper at a thickness of about 5 μm is provided on a minute wiring structure portion formed of aluminum wires at a thickness of about 0.5 μm. This paper describes that the voltage caused by the drop of a voltage by wire resistance can be reduced to ⅕ as compared with normal LSI wiring.
In semiconductor devices, insulating materials called as low-k materials having a low specific inductive capacity of 2.5 or less are being adopted to implement high-speed operation. Furthermore, in consideration of environmental concerns, Pb-free soldering materials are being adopted as materials of soldering balls. With respect to the semiconductor device provided with the huge wiring structure portion disclosed in the above paper, application of the low-k materials and the Pb-free soldering balls to the semiconductor device has been expected.
However, the low-k materials are lower in mechanical strength such as hardness, elasticity, etc., than silicon oxide, silicon nitride, silicon oxynitride, etc. Furthermore, the Pb-free soldering materials are lower in the creep characteristic indicating ease in deformation of material as compared with conventional Pb-Sn type eutectic soldering materials. Therefore, the deformation amount of the soldering ball itself after solidification is small, and thus the residual stress in the soldering ball is increased.
As described above, with respect to the semiconductor devices using the low-k materials and the Pb-free soldering balls, the residual stress in the soldering balls which occurs in the mounting process and the thermal stress occurring in use cause breaking at the connection portions containing soldering balls or brittle fracture, exfoliation, cracks, etc., of the low-k materials which are weak in mechanical strength, and there is concern that it is difficult to secure reliability when packages are fabricated or semiconductor devices are practically used.
A semiconductor chip is generally used as a semiconductor device (package) while mounted on a print board or a mount board such as a build-up substrate or the like. The semiconductor device is mainly used for FCBGA (Flip Chip Ball Grid Array) packages used in applications which require a stable supply of a power supply voltage and adaptation to high speed signals, and compact electronic equipment such as cellular phones, digital cameras or the like, and wafer level CSP (Chip Size Package) formed in substantially the same size as the semiconductor chip, etc., are known. In these packages, various devices have been made to relieve the thermal stress described above. For example, Japanese Published Unexamined Patent Application No. 74417/1999 discloses an FCBGA package in which a semiconductor chip is connected to a BGA board by soldering bumps and under fill resin is filled between the semiconductor chip and the BGA board to protect minute soldering bump connections.
Furthermore, Japanese Published Unexamjined Patent Application Nos. 204560/1999, 2000-150716 and 2000-323628 discloses wafer level CSP in which a low elasticity layer is provided on a semiconductor chip and an external electrode terminal is provided on the low elasticity layer.
FIG. 1 is a perspective view showing a conventional semiconductor device disclosed in Japanese Published Unexamined Patent Application No. 204560/1999. As shown in FIG. 1, in the semiconductor device disclosed in Japanese Published Unexamined Patent Application No. 204560/1999, a plurality of semiconductor devices (not shown) are formed at the center of the surface of a semiconductor chip 101. Pads 104 are provided on these semiconductor devices. Furthermore, a resin layer 102 formed of insulating material is provided on the surface of the semiconductor chip 101 so as to expose the pads 104 and cover the portion other than the center. Furthermore, a low elasticity layer 103 formed of insulating material having low elasticity is provided on the resin layer 102 so as to expose the pads 104. The low elasticity layer 103 has a wedged sectional shape, which is inclined with respect to the center of the surface of the semiconductor chip 101 on which the pads 104 are disposed. External electrode terminals 106 serving as external electrodes for inputting or outputting signals between the semiconductor chip 101 and external equipment are formed on the flat portion of the low elasticity layer 103, and the external electrode terminals 106 and the pads 104 are connected to one another via wiring layers 105. Protection film 108 is formed on the semiconductor chip except for the external electrode terminals 106. Soldering balls 107 serving as projecting electrodes are provided on the external electrode terminals 106. As described above, by providing the low elasticity layer 103 at the lower side of the soldering balls 107, the stress imposed on the soldering balls 107 can be relieved. Furthermore, the soldering balls 107 are provided on the surface of the semiconductor chip 101 so as to be spaced from the pads at a large distance, whereby the stress occurring in the soldering balls 107 can be prevented from being transmitted to the semiconductor device connected to the pads 104.
FIG. 2 is a cross-sectional view showing a conventional semiconductor device disclosed in Japanese Published Unexamined Patent Application No. 2000-150716. As shown in FIG. 2, in the semiconductor device disclosed in Japanese Published Unexamined Patent Application No. 2000-150716, connection terminals 202 are provided on the surface of the semiconductor chip 201. Furthermore, a resin layer 203 and a low elasticity layer 204 are provided at the portions other than the connection terminals 202 on the surface of the semiconductor chip 201. Soldering balls 206 are provided via a wiring layer 205 on the resin layer 203. The wiring layer 205 is connected to the connection terminals 202. The low elasticity layer 204 is formed only at the lower side of the surrounding portion of each soldering ball 206. By providing the low elasticity layer at the lower side of the periphery of each soldering ball as described above, the stress occurring in the soldering ball can be relieved.
Furthermore, FIG. 3 is a cross-sectional view showing a conventional semiconductor device disclosed in Japanese Published Unexamined Patent Application No. 2000-323628. As shown in FIG. 3, in the semiconductor device disclosed in Japanese Published Unexamined Patent Application No. 2000-323628, an electrode 302 is provided on the surface of a semiconductor chip 301. Passivation film 303 is provided so as to cover the semiconductor chip 301 except for the electrode 302, and a resin layer 304 is provided on the passivation film 303. A soldering ball 307 is provided via a wiring layer 306 on the resin layer 304. The electrode 302 is connected to the wiring layer 306. Furthermore, a resin layer 305 is formed so as to cover the surfaces of the resin layer 304 and the wiring layer 306 and the side surface of the lower portion of the soldering ball 307. According to Japanese Published Unexamined Patent Application No. 2000-323628, low elasticity material is used as the resin layer 305 covering the side surface of the soldering ball, so that the stress occurring in the soldering ball can be relieved.
Furthermore, Japanese Published Unexamined Patent Application No. 2003-204169 discloses a technique that a member having flexibility which is obtained by laminating a high elasticity layer and a low elasticity layer is used as a multilayered wiring plate on which a semiconductor chip is mounted. According to this technique, the wires of the multilayered wiring plate and via-holes can be made to be difficult to damage by the thermal stress in use.
Still furthermore, FIG. 4 is a plan view showing another conventional semiconductor device. In the conventional semiconductor device shown in FIG. 4, a plurality of circular external terminals 402 are arranged in a matrix form on a surface layer 401. These external terminals 402 are provided in conformity with high-density minute wires, and the size and pitch of the external terminals 402 are minute.
However, the above conventional techniques have the following problems. In the technique disclosed in Japanese Published Unexamined Patent Application No. 74417/1999, the rigidity of the soldering ball connection portions is enhanced by using the under fill resin, thereby preventing the breaking of the soldering ball connection portions. Therefore, in the semiconductor device provided with the huge wiring structure portion, stress which is not relieved propagates through huge wires serving as rigid bodies and concentrates on the minute wiring structure portion, which may cause breaking of minute wires, breakdown or exfoliation of the insulating film formed of the low-k material, etc.
In the technique disclosed in Japanese Published Unexamined Patent Application No. 204560/1999, the soldering balls are provided so as to be spaced from the pads at a large distance in order to prevent the stress occurring in the soldering balls from propagating to the semiconductor device connected to the pads, and thus an extra space is required to be provided on the surface of the semiconductor chip. In a flip chip mounting semiconductor chip whose number of terminals is increased, it is difficult to secure a space for keeping the soldering balls spaced from the pads and a space for drawing a wiring pattern therefore.
Furthermore, in the technique disclosed in Japanese Published Unexamined Patent Application No. 2000-150716, the low elasticity resin is provided at the lower side of the soldering ball connection portion. However, this low elasticity resin is constrained by the surrounding high elasticity resin, and thus it is impossible to deform the low elasticity resin to the extent that the stress can be relieved, so that the stress relieving is insufficient. Therefore, the stress propagates through the huge wires serving as the rigid bodies and concentrates on the minute wiring structure portion, which may cause breaking of the minute wires, the breakdown or exfoliation of the insulating film formed of the low-k material, etc.
Still furthermore, in the technique disclosed in Japanese Published Unexamined Patent Application No. 2000-323628, the low elasticity resin is provided at the side surface of the soldering ball and the deformation of the soldering ball is promoted to relieve the stress. However, as in the case of the Japanese Published Unexamined Patent Application No. 2000-150716, the stress relieving is insufficient, which causes breaking of the minute wires, breakdown or exfoliation of the insulating film formed of the low-k material, etc.
Still furthermore, in the technique disclosed in Japanese Published Unexamined Patent Application No. 2003-204169, the reliability of the multilayered wiring plate on which the semiconductor chip is mounted is enhanced, however, it is difficult to relieve the stress occurring at the semiconductor chip side.
In the conventional semiconductor device shown in FIG. 4, the size and pitch of the external terminals on the mounting surface are minute, and thus the connection area between the semiconductor device and the mount board when the semiconductor device is mounted on the mount board is small, and thus the connection reliability is lowered.